As silicon device geometries shrink, IC chip densities and speed performance improve considerably. Systems with these devices switch in subnanosecond times with further advances in chip densities and performance being expected. This high speed switching results in high transient currents which cause supply voltage variations, generally known as power supply bounce. In response, decoupling capacitors have generally been used to isolate the devices from the power supply bounce.
Decoupling capacitors have been provided on chip carriers, modules which carry multiple IC chips. See, e.g., U.S. Pat. No. 5,134,539 to Tuckerman et al. and U.S. Pat. No. 4,675,717 to Herrero et al. However, due to the rapidly shrinking sizes and rapidly increasing speeds of integrated circuits, chip carrier decoupling capacitors do not sufficiently reduce or isolate the power supply bounce on the IC chips which it carries. Off-chip decoupling capacitors have been provided with wiring directly to the IC chip. However, the long wire connections have high resistance which necessarily limits the effectiveness of this capacitance due to the excessively large time constant. Also this technique leads to high costs due to discrete capacitor substrate complexity and assembly cost.
On-chip solutions have been attempted by fabricating parallel plate capacitor structures using two or more metal layers of an integrated circuit. For example, in Beach et al., High Dielectric Constant On-Chip Decoupling Capacitor Incorporated Into BEOL Fabrication Process, IBM Technical Disclosure Bulletin, October 1994, a decoupling capacitor is built between the final metal layer and the underlying metal layer. In U.S. Pat. No. 5,208,725 to Akcasu, an integral decoupling capacitor consisting of two sets of parallel conducting strips formed by the existing layers of an integrated circuit is disclosed. These techniques use significant numbers of metal wires that could otherwise be used for signal or logic wiring. A third decoupling capacitor fabrication technique utilizes structures built with gate oxide capacitors. These capacitors occupy a large silicon area of a chip and are prone to stress failure, thereby limiting yield and/or reliability. For example, if the oxide layer is not as thick as desired, a stress point may develop and, with time, cause the chip to fail. In addition, the oxide layer may have a thin hole or other defect which could cause the chip to fail immediately. Thus, these decoupling capacitors are inefficient and expensive.
There is an intensely felt need in the integrated circuit industry to provide a low cost and highly reliable integrated circuit having an integral decoupling capacitor. The present invention addresses this need as well as other needs.